Michael Dossis
The advancing complexity of contemporary microelectronics has motivated research in high-level and system synthesis (HLS). Formal and intelligent HLS techniques are presented in this contribution, thus the generated implementation is correct-by-construction. These intelligent techniques include RDF (Resource Description Framework) and logic relations, along with automatic implementation options and they are employed for the transformations of a hardware compiler. The proposed toolset utilizes compiler-generators, RDF rules and logic programming in combination with XML validation of the internal state of the compiler. These intelligent and formal techniques make the whole transformation from source code to implementation, formal. The HLS tool is enhanced with the Parallel, Abstract Resource – Constrained Scheduler, which aggressively optimizes the initial state schedules, into maximally parallelized ones. A number of custom options are applied by the user of this toolset, in order to automatically compile selected testcases from real-world applications which prove the usability of the embedded scheduler and the formal compilation of the intelligent HLS compiler.
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