Journal of Electrical & Electronic Systems

Sathyavathin S

Publications

• Research Article
  A Novel Voltage-Mode Lut Using Clock Boosting Technique in Standard CMOS
  Author(s): Sathyavathin S and Mr Ilanthendral JSathyavathin S and Mr Ilanthendral J
  
  In a VLSI circuit, interconnection plays the dominant role in every part of the circuit nearly 70 percent of the area depends on interconnection, 20 percent of area depends on insulation, and remaining 10 percent to devices. The binary logic is limited due to interconnect which occupies large area on a VLSI chip. In this work, the designs of quaternaryvalued logic circuits have been explored over multi-valued logic due to the following reasoning. An approach to mitigate the impact of interconnections is to use multiple-valued logic (MVL), hence, more information can be carried in each wire, reducing the routing network. Therefore, a single wire carrying a signal with N logic levels can replace log N having base 2 wires carrying binary signals. Reducing the routing leads to a direct reduction of the line capacitance and the overall circuit area. Therefore, this results in increasing th.. Read More»
  DOI: 10.4172/2332-0796.1000139

  Abstract PDF