Unity Gain and Variable Gain OTA Buffer Amplifier with Resistive Load Using Multi-Gate Transistors

Remya Jayachandran^* and Rama S Komaragiri
^*Correspondence: Remya Jayachandran, Department of Electronics and Communication, The National Institute of Engineering Mysore, Karnataka, India, Email:

Keywords

Buffer amplifier • OTA • Resistive load • SG-RFET • GAAFET

Introduction

Buffer amplifier circuits using operational amplifiers are commonly used as buffer circuits in analog signal processing applications for driving heavy resistive loads. Unity gain buffer amplifier using OTA is the most fundamental driving scheme used in LCD column drivers to drive large capacitive loads [1]. Biomedical, video and telecommunication applications require a buffer amplifier capable of driving heavy resistive loads preferably with a variable gain. DC coupling is required to drive heavy resistive loads (typically below 100 Ω) which complicates the buffer design. While driving a heavy resistive load, a trade-off exists among voltage gain, output swing, and power consumption that sets the performance limits on the existing buffer circuit designs.

The rapid development of smart phones and other electronic gadgets has forced a significant downscaling in the physical size of devices. The increased demand for high-speed, low- power devices and compactible devices has replaced the planar MOSFET with new device architectures and materials. As device dimension shrinks, gate control over the channel of planar transistors becomes more difficult. The conventional planar MOSFETs are replaced by new device architectures such as multi- gate devices, carbon nanotubes, tunnel FETs, single- electron devices, reconfigurable FETs to meet the demands for high speed, compatible and low power consumption [2-9]. Among these, Reconfigurable Field- Effect Transistor (RFET) is an emerging multi-gate device. RFET can be configured as an n-type FET or a p-type FET by applying an appropriate bias to the terminals. Fabrication of the RFET device is less complex compared to the existing MOS transistors, as there is no need for doping.

RFET device structures with triple gate, double gate and single gate are reported in literature [10-14]. A simple and high-performance RFET with a single control gate RFET (SG-RFET) [13]. Compared to triple gate RFET and polarity gate RFET, SG-RFET has a very simple structure. The structure of SG-RFET device is similar to the multigate Device Gate-All-Around FET (GAAFET). In GAAFET, the gate material extends to surround the channel on all sides in order to attain maximum electrostatic integrity. Cylindrical type GAAFET offers the lowest natural length which leads to further scaling of the device. Because of the special architecture of GAA device, carrier conduction is not limited through Si/SiO₂ interface but it is through the center of the device. This in turn reduces the interface related issues in device modeling. The device dimensions are gate dielectric thickness (tox), channel length (LG) and channel diameter (tsi).

Digital circuits realized using RFET device is found in literature [8, 15-28]. The results show good performance and is comparable with the other multigate transistors. In, RFET is realized on a planar fully depleted (FD)- SOI device and the electrostatics and the performance of the device are studied and compared with the standard 28 nm FD-SOI [15]. Highfrequency analog applications using the double-gate and single-gate RFET [16]. In, reconfigurable circuits using polarity controlled double gate RFET with excellent performance are reported and a two-transistor fully functional XOR gate is demonstrated for the first time [17]. In, inverter circuits based on the Gate All Around FET (GAAFET) with elliptical cross-section are analyzed to observe an improvement in the delay of the circuits compared to a circular cross-section device [18]. In, performance analysis of logic gates using polarity controlled RFET [19, 20].

Experimental demonstration of current mirrors using silicon nanowire transistors in inversion and the sub-threshold region [21]. In, silicon channel is replaced by germanium, which resulted in a low power dissipation due to reduced series resistance [22]. A ring oscillator circuit and in analog and digital circuits implemented using tunnel FET with an astounding performance at low supply voltage [23, 24]. RFET with strained silicon to improve the mobility [25]. The performance analysis of a single gate to triple gate RFET [26]. A top-down fabrication of RFET with symmetric transfer characteristics that exhibits minimal hysteresis, high on- and low off-currents for both, n and p configuration [27]. The electron transport through NiSi2- Si contacts in the RFET [28]. In, current mirrors are demonstrated for the first-time using SG-RFET device with reconfigurable nature [8]. However, the analog circuits using the RFET device are not found in the literature. Buffer amplifier circuit capable of driving resistive loads are required in many analog signal processing applications. Hence, buffer circuit designed using new device architectures - SG-RFET and GAAFET, help to analyses the feasibility of using SG-RFET and GAAFET device in analog circuits.

Unity gain buffer configuration-buffer 1 is implemented using SG-RFET device and GAAFET device and compared with the buffer 1 implemented using OTA IC LM13700 [29]. In this paper, unity gain buffer 2 configurations proposed in and variable gain buffer circuit proposed in with resistive load using SG-RFET device and GAAFET [29, 30].

Unity Gain OTA Buffer Using SG-RFET Inverter and GAAFET Inverter Circuit

The detailed study of the OTA buffer amplifiers using MOSFET [29]. The load driving capability is increased by increasing the gm of OTA. A unity gain buffer amplifier circuit-buffer 2 using OTA with improved load driving capability and wide bandwidth [29].

Structure of SG-RFET and GAAFET simulated in TCAD Sentaurus is shown in Figure 1 [30]. A two-stage buffer amplifier circuit using OTA is realized using SG-RFET OTA and GAAFET OTA in Sentaurus TCAD tool. Due to the dense meshing at the interface regions in the device, it is difficult to simulate the circuit with more components in Sentaurus TCAD tool. The OTA configuration used in the simulation is Nauta’s OTA as it contains only inverter blocks. To minimize the complexity in computation, two-stage buffer 2 configuration is implemented using the non-planar devices- SG-RFET and GAAFET and analyzed the output. Using sdevice module in TCAD, electrical characterization of the two-stage unity gain OTA buffer circuit is carried out with resistive load. Buffer 2 configuration can drive heavy resistance loads as the output impedance of the configuration decreases with the increase in the number of stages N.

The circuit parameters used in the simulation are supply voltage VDD = 2 V, output load resistance, RL = 1 kΩ, input sinusoidal signal amplitude, Vpp = 0.5 V, and frequency 1 kHz. For two-stage buffer 2 using SG-RFET OTA and GAAFET OTA, a peak-to-peak amplitude of 0.495 V is obtained as output from the simulation results, that results in a gain of 0.99 V/V. As the RL reduces, the buffer circuit’s gain reduces as expected. The hardware of the two-stage OTA buffer circuit is implemented using OTA LM13700 IC and verified the performance. Depicts the simulation results of buffer 2 configuration implemented using different OTAs (Table 1). The performance of the SG-RFET OTA buffer amplifier is compared with GAAFET OTA and CMOS OTA. GAAFET buffer 2 configuration exhibits a wide bandwidth compared to other configurations.

Table 1: Two-stage buffer 2 configuration with resistive load.

Variable Gain Analog Buffer Amplifier

The OTA based unity gain analog buffer amplifier circuit is modified by applying a feedback voltage as shown in Figure 2. Tunable gain OTA buffer amplifier is presented in using CMOS OTA [29]. In this section, design of a simple variable gain buffer amplifier implemented using SG-RFET, GAAFET OTA and OTA IC LM13700 are presented.

The feedback factor of the buffer configuration is:

Here go, B, Av are output conductance, feedback factor and gain respectively. The feedback factor depends on the gain and the output load of the proposed configuration. Shows the variation in gain with respect to the feedback factor with a 1 kΩ as the output load (Figure 3) [30].

The feedback circuit is implemented using the buffer 1 with a resistive load to obtain the required feedback voltage. The desired gain is achieved by varying the feedback voltage. The feedback factor depends on both the gain and output load that reduces the maximum output swing. The design simplicity makes the proposed configuration useful in biomedical, video and telecommunication applications. The limitation of this configuration is its low input dynamic range, and the area requirement for large gm OTAs to drive low-resistance load. In this work, the functionality of the buffer circuit is verified using the OTA IC-LM13700 [9]. The gain variation with respect to changes in feedback voltage is observed at a particular resistance load. represents the circuit parameters of the OTA IC -LM13700, GAAFET-OTA and this work (Table 2). The proposed circuit is implemented using OTA LM13700 IC.

Table 2: Buffer amplifier circuit parameters.

Depicts the circuit parameters of the different OTA buffer amplifiers. The tunable gain represents the maximum gain possible for the proposed buffer configuration. Shows the buffer amplifier circuit parameters used in simulations.

The simple design, low fabrication complexity, reconfigurable property and reduced area make SG-RFET outperform the existing devices. The trade-off is speed and supply voltage. Supply voltage greater than 1.5 V is required to obtain high ION /IOF F ratio. By using SiGe or Germanium instead of silicon, the drain current of an SG-RFET can be improved thus enabling low voltage operation [31]. Compared to SG-RFET OTA buffer circuits, GAAFET OTA buffer has wide bandwidth (Figure 4).

Conclusion

In this paper, two-stage buffer 2 configuration and a simple OTA buffer amplifier circuit with a variable gain is presented. The OTA buffer is implemented with SG-RFET OTA and GAAFET OTA in Sentaurus TCAD, and the simulation results and functionality are verified using the LM13700 OTA IC. Hardware implementation of the simple variable gain buffer circuit is carried out using the LM13700 OTA IC to verify the functionality of the circuit. SG-RFET buffer amplifier exhibits good characteristics with a gain tunability of up to 5 V/V for 1 kΩ load. GAAFET buffer circuit has a wide bandwidth and gain tunability up to 5 V/V for 1 kΩ load. Variable gain buffer amplifier circuit using the SG-RFET device and GAAFET device indicate the design flexibility on analog circuits in analog signal processing applications.

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